Programmable frequency dividers are widely deployed in applications such as clocking and frequency synthesis. Programmable frequency dividers have been developed that have a 50% duty cycle and that operate at relatively high clock speeds. However, there is a need for programmable frequency dividers that operate at even higher clock speeds. While programmable frequency dividers are relatively easy to design that either operate at high input frequencies (multi-GHZ) or that have 50% output duty cycle, it is difficult to design a programmable frequency divider that both operates at multi-GHZ clock frequencies and has a 50% duty cycle. This is especially true when the division ratio (divisor) is odd because the frequency divider must be able to count in half-cycles to achieve a 50% duty cycle. Frequency dividers that count in half cycles are more complex, use more die area, and require more power than frequency dividers that do not count in half-cycles.
Accordingly, there is a need for a programmable frequency divider that can operate at high input frequencies, that has a 50% output duty cycle and that does not have the complexity and power requirements of conventional frequency dividers that count in half cycles.